Type of Document	Thesis
Author	Jones, Kelley C
Author's Email Address	kelleyj@gmail.com
URN	etd-04042007-200021
Title	Graphical Visualization of Architectural Simulators
Degree	Master of Science
Department	Computer Science, Department of
Advisory Committee	Advisor Name Title David Whalley Committee Co-Chair Gary Tyson Committee Co-Chair Xin Yuan Committee Member
Keywords	User Interface Debugging Visualization Tool Computer Architecture
Date of Defense	2007-04-04
Availability	unrestricted
Abstract This thesis describes an architectural visualization tool developed to illustrate the instruction flow in a modern processor pipeline simulation. It was designed to aid in better understanding the complexities of a modern pipeline design. The visualizer allows the user to control the execution of the simulator by stepping ahead cycles in execution as well as setting breakpoints and watchpoints on microarchitected state data. The visualizer can also display the contents of microarchitected state at any time, enabling careful analysis of the state of the simulator. We believe that these features within the visualizer will allow a developer to more easily analyze the effects of a new compiler optimization or microarchitectural addition in more depth than typical simulator statistical data provides. Furthermore, we feel the visualizer is a valuable teaching aid in computer architecture classes, as it allows students to interactively visualize the control and data flow of a program through a particular pipeline design. Lastly, the visualizer was created in such a way to provide easier interfacing to other simulators.
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