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Type of Document Thesis Author Ambre, Mandar Shriram Author's Email Address ambre@eng.fsu.edu URN etd-04122004-164143 Title A Design Methodology for the Implementation of Fuzzy Logic Traffic Controller using Field Programmable Gate Arrays Degree Master of Science Department Electrical and Computer Engineering, Department of Advisory Committee
Advisor Name Title Bing Kwan Committee Chair Simon Foo Committee Member Uwe Meyer-Baese Committee Member Keywords
- Traffic Controller
- Fuzzy Logic
- Field Programmable
- Gate Arrays
Date of Defense 2004-04-02 Availability unrestricted Abstract In this thesis, an approach is proposed for the design and implementation of fuzzy traffic controllers using Field Programmable Gate Arrays (FPGAs).The focus of this study is to develop an effective traffic signaling strategy to be implemented at a typical intersection with four approaches. Adaptive traffic control using fuzzy principles has been demonstrated and reported by the authors in the literature. Here a high-level design approach is suggested, which involves VHDL-based logic synthesis and the use of state diagrams with a VHDL backend for graphical design description. The operations of the fuzzifier and the defuzzifier of the fuzzy controller are described in VHDL. The fuzzy rule base for the controller is described using the state diagrams. Specifically, the fuzzy inference based on the fuzzy rules is implemented using MATLAB code. The output of the MATLAB program is stored in a ROM for use in the VHDL code. Once VHDL code is obtained then the hardware is implemented using the UP1 Education board. After the design was tested by using UP1 board the next step was to design a printed circuit board for this system. This was done by using Protel Design Explorer where the input to the circuit board comes from traffic sensors in the field and the output of the circuit board is given to the traffic controller.Files
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28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access Preliminary_pages.pdf 2.27 Mb 00:10:31 00:05:24 00:04:43 00:02:21 00:00:12 Thesis.pdf 3.11 Mb 00:14:23 00:07:23 00:06:28 00:03:14 00:00:16