Type of Document	Thesis
Author	West, Paul E
Author's Email Address	west@cs.fsu.edu
URN	etd-04142008-113042
Title	Core Monitors: Monitoring Performance in Multicore Processors
Degree	Master of Science
Department	Computer Science, Department of
Advisory Committee	Advisor Name Title Andy Wang Committee Member David Whalley Committee Member Gary Tyson Committee Member
Keywords	Multicore Architecture
Date of Defense	2008-04-09
Availability	unrestricted
Abstract Performance counters are becoming more complex as multi-core systems are becoming more wide spread. Consequently, evaluating these counters has become more complex as well. We propose providing hardware that monitors performance counters, namely in multi-core systems, in order to make decisions for improving performance. For instance, a piece of hardware watching snoop packets may be able to determine when a write-update cache coherence protocol would be helpful or detrimental to the current running program. Furthermore, watching memory traffic through a shared cache can determine if a program on a certain CPU is memory-bound. Once a program on a CPU is determined memory bound, the kernel can be informed to schedule accordingly. Finally, these new counters may be used to facilitate obtaining profile data for the compiler. We have implemented monitors in a full system simulator and found performance improvement.
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