Type of Document Thesis Author Natarajan, Hariharan URN etd-04202004-002332 Title Implementation of Chirp z DFT on Virtex II FPGA Degree Master of Science Department Electrical and Computer Engineering, Department of Advisory Committee
Advisor Name Title Uwe Meyer-Baese Committee Chair Anke Meyer-Baese Committee Member Simon Foo Committee Member Keywords
- Virtex II
Date of Defense 2004-04-09 Availability unrestricted AbstractThe application of Fourier results in conversion in representation of a signal in time domain to frequency domain. Hence, it forms an important tool for frequency analysis. With advent of digital computers, we can perform frequency analysis faster and more efficiently. Thus discrete Fourier transform is important for frequency analysis of signal in discrete form.
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) algorithms have been invented in several variations. This thesis focuses on implementation of the Bluestein Chirp-z transform algorithm. This method uses chirp signals, which are complex exponential signals, which increase linearly with time. Hence, the name chirp-z Transform. The transform is implemented on Xilinx Inc.’s Virtex II FPGA. Virtex II family has two of the world’s largest programmable device with gate count up to 8 million. It’s features like embedded multiplier and memory make it ideal for digital signal processing applications. The implementation of chirp-z transform would involve designing a ROM to store the twiddle factors; a complex number multiplier and FIR filter for convolution. Again, we look at various algorithms for calculation of filter coefficient for minimum cost of adder and multiplier.
DFT are implemented for length 4 point, 16 point, 32 point and 64 point. We analyze each of the above-mentioned implementations and especially the space occupied and the speed of the device.
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