Type of Document	Thesis
Author	Sunkara, DivyaLakshmi
Author's Email Address	divyalakshmi_sunkara@yahoo.com
URN	etd-06262004-162018
Title	Design of Custom Instruction Set for FFT using FPGA-Based Nios Processors
Degree	Master of Science
Department	Electrical and Computer Engineering, Department of
Advisory Committee	Advisor Name Title Dr. Uwe Meyer-Baese Committee Chair Dr. Anke Meyer-Baese Committee Member Dr. Shonda Walker Committee Member
Keywords	CPLD FPGA Embedded processor Soft-core microprocessor Radix-2 FFT RISC Architecture.
Date of Defense	2004-06-17
Availability	unrestricted
Abstract Nios Embedded processors provide a powerful, robust platform for developing and implementing complex algorithms. The unique custom instruction feature of Nios processors could be used to enhance the performance of these algorithms dramatically, while reducing the size and complexity of software. This feature involves implementing a part or entire algorithm in hardware and making it accessible to software through specially generated software macros known as custom instructions. Currently, fast Fourier transform (FFT) algorithms play an important role in many of the digital signal processing applications that are highly time critical. Hence there is a need to increase the performance of these algorithms. In the thesis, the decimation-in-frequency radix-2 FFT is implemented using custom instruction for the butterfly processor present in the algorithm. The performance enhancement of the custom implementation of this algorithm is then measured against software-only implementation.
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