Type of Document	Thesis
Author	Petrone, Joseph G
URN	etd-07062004-133258
Title	Adaptive Filter Architectures For FPGA Implementation
Degree	Master of Science
Department	Electrical and Computer Engineering, Department of
Advisory Committee	Advisor Name Title Simon Foo Committee Chair Anke Meyer-Baese Committee Member Uwe Meyer-Baese Committee Member
Keywords	System-On-Chip LMS Fpga Filter Adaptive
Date of Defense	2004-06-29
Availability	unrestricted
Abstract Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. Furthermore, some manufacturers now include complete microprocessors within the FPGA fabric. This mix of hardware and embedded software on a single chip is ideal for fast filter structures with arithmetic intensive adaptive algorithms. This thesis aims to combine efficient filter structures with optimized code to create a System-on-chip (SoC) solution for various adaptive filtering problems. Several different adaptive algorithms have been coded in VHDL as well as in C for the PowerPC 405 microprocessor. The designs are evaluated in terms of design time, filter throughput, hardware resources, and power consumption.
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