Type of Document Dissertation Author Zhao, Wankang Author's Email Address email@example.com URN etd-07182005-105747 Title Reduing the WCET of Low End Embedded Applications Degree Doctor of Philosophy Department Computer Science, Department of Advisory Committee
Advisor Name Title David Whalley Committee Chair Keywords
Date of Defense 2005-07-11 Availability unrestricted AbstractApplications in embedded systems often need to meet specified timing constraints.
It is advantageous to not only calculate the Worst-Case Execution Time (WCET) of
an application, but to also perform transformations that attempt to reduce the
WCET, since an application with a lower WCET will be less likely to violate its
A compiler has been integrated with a timing analyzer
to obtain the WCET of a program on demand during compilation. This environment is used
to investigate three different types of compiler optimization techniques to reduce
First, an interactive compilation system has been developed that allows a user to
interact with a compiler and get feedback regarding the WCET.
In addition, a genetic algorithm is used to automatically search
for an effective optimization phase sequence to reduce the WCET.
Second, a WCET code positioning optimization has been investigated that uses
worst-case path information to reorder basic blocks so that the branch penalties
can be reduced in the worst-case path.
Third, WCET path optimizations, similar to frequent path optimizations, are used
to reduce the WCET.
There are several contributions to this work.
To the best of our knowledge, this is the first compiler that
interacts with a timing analyzer to use WCET predictions during the
compilation of applications.
The dissertation demonstrates that a genetic algorithm search can find
an optimization sequence that simultaneously improves both WCET
and code size.
New compiler optimizations have
been developed that use WC path information from
a timing analyzer.
The results show that the WCET code positioning algorithm typically
finds the optimal layout of the basic blocks with the minimal WCET.
It is also shown that frequent path optimizations
can be applied on WC paths using worst-case path information from
a timing analyzer to reduce WCET.
These new compiler optimizations described in this dissertation
not only significantly reduce WCET, but also are completely automatic.
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