Type of Document	Thesis
Author	Wall, Geoffrey Warren
URN	etd-11102008-142147
Title	Embedded Pattern Recognition with Field Programmable Gate Arrays
Degree	Master of Science
Department	Electrical and Computer Engineering, Department of
Advisory Committee	Advisor Name Title Simon Y. Foo Committee Chair Uwe Meyer-Baese Committee Member Xiuwen Liu Outside Committee Member
Keywords	Digital Logic Embedded System Design Computer Vision Pattern Recognition FPGA
Date of Defense	2007-02-22
Availability	unrestricted
Abstract Field programmable gate arrays (FPGAs) are becoming increasingly prevalent in embedded digital signal processing applications. Faster clock speeds (now at 500 MHz), greater logic density, and dedicated embedded DSP hardware blocks are facilitating signal processing performance up to 1000 times faster than modern microprocessors. Improved computer aided design tools are allowing logic designers to implement ever more complex algorithms in eld programmable logic. This thesis will present the design and implementation details of a pattern classication algorithm specically tuned for implementation in an FPGA's recongurable fabric. The recongurable solution presented compares favorably with a desktop PC based implementation when considering classication throughput. Additionally, the FPGA based system has power and space requirements roughly two orders of magnitude smaller than the PC, thus making it a more suitable candidate for embedded applications.
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