Type of Document	Thesis
Author	Gavin, Peter Brendan
Author's Email Address	gavin@cs.fsu.edu
URN	etd-11162010-105319
Title	Instruction Caching in Multithreading Processors Using Guarantees
Degree	Master of Science
Department	Computer Science, Department of
Advisory Committee	Advisor Name Title Gary S. Tyson Committee Chair David B. Whalley Committee Co-Chair Xin Yuan Committee Member
Keywords	Simultaneous Multithreading Low Power
Date of Defense	2010-10-29
Availability	unrestricted
Abstract The OpenSPARC T1 is a multithreading processor developed and open sourced by Sun Microsystems (now Oracle). This paper presents an implementation of the low-power Tagless-Hit Instruction Cache (TH-IC) for the T1, after adapting it to the multithreading architecture found in that processor. The TH-IC eliminates the need for many instruction cache and ITLB accesses, by guaranteeing that accesses within a much smaller L0-style cache will hit. The OpenSPARC T1 uses a 16KB, 4-way set associative instruction, and a 64-entry fully associative ITLB. The addition of the TH-IC eliminates approximately 75% of accesses to these structures, instead processing the fetch directly from a much smaller 128 byte data array. Adding the TH-IC to the T1 also demonstrates that even already power efficient processors can be made more efficient using this technique.
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