Type of Document	Thesis
Author	Patronis, Sean Gregory
URN	etd-12112008-135228
Title	Sparse FIR Filters And The Impact On FPGA Area Usage
Degree	Master of Science
Department	Electrical and Computer Engineering, Department of
Advisory Committee	Advisor Name Title Linda DeBrunner Committee Chair Bruce Harvey Committee Member Victor DeBrunner Committee Member
Keywords	Area Utilization FPGAs Sparse FIR Filters
Date of Defense	2008-12-03
Availability	unrestricted
Abstract In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area, and maybe speed up computations, but to implement the same sparse filter in an FPGA, the same area savings may not be realized. The research conducted in this work concentrated on creating sparse FIR filters where groups of non zero coefficients replaced by zeros were synthesized on Xilinx Virtex-4 FPGAs. Custom MatlabŪ functions were written in which different patterns of zero placements were populated on top of a base set of coefficients. These coefficient files were then used with custom PHP based code to generate VHDL files defining FIR filters. The FIR filters built in VHDL were synthesized in Xilinx ISE. After synthesis, data pertaining to area usage was then collected and analyzed. We conclude that sparsity in an FIR filter may not translate directly into FPGA space (area) savings on a Virtex-4 FPGA depending on order, sparsity and FPGA chip used.
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