Type of Document	Thesis
Author	Howard, Charles David
URN	etd-12132008-092342
Title	Minimizing FIR Filter Designs Implemented in FPGAs Utilizing Minimized Adder Graph Techniques
Degree	Master of Science
Department	Electrical and Computer Engineering, Department of
Advisory Committee	Advisor Name Title Linda S. DeBrunner Committee Chair Bruce A. Harvey Committee Member Victor DeBrunner Committee Member
Keywords	Adaptive Filters Multiplier Block Directed Graph Multiplierless Field Programmable Gate Arrays
Date of Defense	2008-12-01
Availability	unrestricted
Abstract Multiple constant multiplications (MCM) is an optimization technique that is well-suited to DSP implementations. Using MCM, all coefficient multiplications are grouped into one efficient block of wired shifts and adds. A disadvantage of using MCM is the requirement of knowing the filter coefficients {it a priori}. Due to this limitation, MCM optimizations cannot be used in many applications. We propose a programmable adder graph (PAG) circuit that can implement multiplication using shift and add techniques without prior knowledge of the multiplier value. The PAG circuit allows any programmable device to be optimized using MCM for a wide range of DSP applications, including adaptive filters.
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